Sub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS / Raviteja Kammari; supervised by Vijay Shankar Pasupureddi.

By:

Kammari, Raviteja [author.]

Contributor(s):

Pasupureddi, Vijay Shankar [supervisor.]

Material type:

TextLanguage: English Publication details: Bhubaneswar : IIT Bhubaneswar, 2026.Description: xxv, 159 p. : illustrations ; 30 cmSubject(s):

DDC classification:

621.3815 RAV/S

Summary: Sub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS: This thesis focuses on the design and development of low-power RF receiver front-ends using sub-sampling mixer-first architectures for beamforming and MIMO wireless communication systems. It addresses major challenges in sub-sampling receivers, including RF-port impedance matching, noise folding, direct down-conversion, harmonic interference, and power consumption. The research investigates how impedance matching can be integrated into mixer-first architectures while maintaining efficient RF signal reception and supporting beamforming applications. Implemented using 1.2 V, 65 nm CMOS technology, the work contributes to compact and energy-efficient RF front-end solutions suitable for modern wireless communication systems and spatial interference mitigation. Related IIT Bhubaneswar work by Kammari and collaborators demonstrates the feasibility of sub-sampling mixer-first architectures with integrated impedance-matching techniques in this CMOS technology.

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Cover image	Item type	Current library	Home library	Collection	Shelving location	Call number	Materials specified	Vol info	URL	Copy number	Status	Notes	Date due	Barcode	Item holds	Item hold queue priority	Course reserves
	PhD Thesis	Central Library, IIT Bhubaneswar	Central Library, IIT Bhubaneswar	SECS		621.3815 RAV/S (Browse shelf(Opens below))					Not for loan			PHD426

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Includes bibliographical references and index.

Sub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS: This thesis focuses on the design and development of low-power RF receiver front-ends using sub-sampling mixer-first architectures for beamforming and MIMO wireless communication systems. It addresses major challenges in sub-sampling receivers, including RF-port impedance matching, noise folding, direct down-conversion, harmonic interference, and power consumption. The research investigates how impedance matching can be integrated into mixer-first architectures while maintaining efficient RF signal reception and supporting beamforming applications. Implemented using 1.2 V, 65 nm CMOS technology, the work contributes to compact and energy-efficient RF front-end solutions suitable for modern wireless communication systems and spatial interference mitigation. Related IIT Bhubaneswar work by Kammari and collaborators demonstrates the feasibility of sub-sampling mixer-first architectures with integrated impedance-matching techniques in this CMOS technology.

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