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Introduction to VLSI design flow / (Record no. 14531)

MARC details
000 -LEADER
fixed length control field	02553cam a22002298i 4500
001 - CONTROL NUMBER
control field	11110
003 - CONTROL NUMBER IDENTIFIER
control field	IN-BhIIT
005 - DATE AND TIME OF LATEST TRANSACTION
control field	20250306181502.0
008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION
fixed length control field	230131s2023 enk b 001 0 eng
020 ## - INTERNATIONAL STANDARD BOOK NUMBER
ISBN	9781009200813 (pbk)
040 ## - CATALOGING SOURCE
Original cataloging agency	IN-BhIIT
041 ## - LANGUAGE CODE
Language code of text	eng
082 00 - DEWEY DECIMAL CLASSIFICATION NUMBER
Classification number	621.395
Book number	SAU/I
100 1# - MAIN ENTRY--AUTHOR NAME
Personal name	Saurabh, Sneh,
Relator term	Author.
245 10 - TITLE STATEMENT
Title	Introduction to VLSI design flow /
Statement of responsibility, etc	by Sneh Saurabh.
260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT)
Place of publication	New York :
Name of publisher	Cambridge University Press,
Year of publication	2024.
300 ## - PHYSICAL DESCRIPTION
Number of Pages	xxiv, 687 p. :
Other physical details(ill.)	ill. ;
Dimensions(size)	24 cm.
504 ## - BIBLIOGRAPHY, ETC. NOTE
Bibliography, etc	Includes bibliographical references and index.
520 ## - SUMMARY, ETC.
Summary, etc	"Chip designing is a complex task that requires an in-depth understanding of VLSI design flow, skills to employ sophisticated design tools, and keeping pace with the bleeding-edge semiconductor technologies. This lucid textbook is focused on fulfilling these requirements for students, as well as a refresher for professionals in the industry. The book consists of four parts. The first part describes foundational concepts related to VLSI design flow and integrated circuits. It also gives an overview of the design, verification, and test methods employed in a typical VLSI design flow. The second part of the book describes the logic implementation and verification steps such as simulation, static timing analysis, and formal methods. It also explains the modelling of hardware using Verilog and logic synthesis; technology libraries; and timing constraints along with logic, power, and timing optimization techniques. The third part of the book describes the design for test (DFT) methods for digital circuits. The fourth and final part describes physical design methods and physical verification. All the physical design implementation steps such as floorplanning, placement, clock-tree synthesis, and routing are described in this part. Moreover, physical verification steps, such as parasitic extraction, design rule checks (DRCs), electrical rule checks (ERCs), layout versus schematic (LVS) checks, and post-silicon validation are explained. Illustrations and pictorial representations are used liberally to simplify the explanation. Additionally, activities are suggested at the end of relevant chapters to help readers gain a practical understanding of VLSI design flow. Review questions and problems are given at the end of each chapter to revise the concepts. Recent trends and references are listed at the end of each chapter for further reading"--
650 #0 - SUBJECT ADDED ENTRY--TOPICAL TERM
Topical Term	Integrated circuits
General subdivision	Very large scale integration.
942 ## - ADDED ENTRY ELEMENTS (KOHA)
Koha item type	Technical Reference Book
Koha issues (borrowed), all copies	1

Holdings
Withdrawn status	Lost status	Damaged status	Not for loan	Collection code	Home library	Current library	Date acquired	Source of acquisition	Cost, normal purchase price	Full call number	Accession Number	Cost, replacement price	Price effective from	Koha item type
Not withdrawn	Not Lost	not damaged			Central Library, IIT Bhubaneswar	Central Library, IIT Bhubaneswar	09/12/2024	22	712.50	621.395 SAU/I	11110	950.00	09/12/2024	Technical Reference Book