000			02031nam a22002657a 4500
001			PHD426
003			IN-BhIIT
005			20260908092708.0
008			260907b |||||||| |||| 00| 0 eng d
040			_aIN-BhIIT
041			_aeng
082			_a621.3815 _bRAV/S
100			_aKammari, Raviteja, _eauthor. _928578
245			_aSub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS / _cRaviteja Kammari; supervised by Vijay Shankar Pasupureddi.
260			_aBhubaneswar : _bIIT Bhubaneswar, _c2026.
300			_axxv, 159 p. : _billustrations ; _c30 cm.
504			_aIncludes bibliographical references and index.
520			_aSub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS: This thesis focuses on the design and development of low-power RF receiver front-ends using sub-sampling mixer-first architectures for beamforming and MIMO wireless communication systems. It addresses major challenges in sub-sampling receivers, including RF-port impedance matching, noise folding, direct down-conversion, harmonic interference, and power consumption. The research investigates how impedance matching can be integrated into mixer-first architectures while maintaining efficient RF signal reception and supporting beamforming applications. Implemented using 1.2 V, 65 nm CMOS technology, the work contributes to compact and energy-efficient RF front-end solutions suitable for modern wireless communication systems and spatial interference mitigation. Related IIT Bhubaneswar work by Kammari and collaborators demonstrates the feasibility of sub-sampling mixer-first architectures with integrated impedance-matching techniques in this CMOS technology.
650			_aRadio frequency circuits _xDesign and construction. _928579
650			_aIntegrated circuits
650			_aCMOS technology. _928580
650			_aMixers (Electronics) _928581
700			_aPasupureddi, Vijay Shankar, _esupervisor. _928582
942			_cTH
999			_c15715 _d15715