000			01865 a2200277 4500
001			TB12457
003			IN-BhIIT
005			20260508183600.0
008			250402b |||||||| |||| 00| 0 eng d
020			_a9783031797422 (PBK.)
040			_aIN-BhIIT
041			_aeng
082			_a621.395 _bREE/I
100			_aReese, Robert _eAuthor _925941
245			_aIntroduction to logic synthesis using verilog HDL / _cby Robert B. Reese and Mitchell A. Thornton
260			_aMorgan : _bSpringer, _c2022.
300			_aVii, 75 p. : _bill. ; _c28 cm
504			_aIncludes bibliographical references and index.
520			_aIntroduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.
650			_aElectronic digital computers _x Circuits _94963
650			_aLogic circuits _94964
650			_aLogic design _94965
650			_aDigital integrated circuits _92923
700			_aThornton, Mitchell A. _eJoint author _925943
942			_cTB _01
999			_c15002 _d15002