01948nam a22002417a 4500001000700000003000900007005001700016008004100033040001300074041000800087082002000095100003200115245017300147260004300320300004300363504005100406520107900457650005501536650002401591650002101615650002501636700004501661PHD426IN-BhIIT20260908092708.0260907b        |||||||| |||| 00| 0 eng d  aIN-BhIIT  aeng  a621.3815bRAV/S  aKammari, Raviteja,eauthor.  aSub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS /cRaviteja Kammari; supervised by Vijay Shankar Pasupureddi.  aBhubaneswar :bIIT Bhubaneswar,c2026.  axxv, 159 p. :billustrations ;c30 cm.  aIncludes bibliographical references and index.  aSub-sampling mixer-first beamforming RF front-ends with integrated impedance matching in 1.2 V, 65 nm CMOS: This thesis focuses on the design and development of low-power RF receiver front-ends using sub-sampling mixer-first architectures for beamforming and MIMO wireless communication systems. It addresses major challenges in sub-sampling receivers, including RF-port impedance matching, noise folding, direct down-conversion, harmonic interference, and power consumption. The research investigates how impedance matching can be integrated into mixer-first architectures while maintaining efficient RF signal reception and supporting beamforming applications. Implemented using 1.2 V, 65 nm CMOS technology, the work contributes to compact and energy-efficient RF front-end solutions suitable for modern wireless communication systems and spatial interference mitigation. Related IIT Bhubaneswar work by Kammari and collaborators demonstrates the feasibility of sub-sampling mixer-first architectures with integrated impedance-matching techniques in this CMOS technology.  aRadio frequency circuitsxDesign and construction.  aIntegrated circuits  aCMOS technology.  aMixers (Electronics)  aPasupureddi, Vijay Shankar,esupervisor.