| 000 | 00688nam a22002177a 4500 | ||
|---|---|---|---|
| 999 |
_c9887 _d9887 |
||
| 001 | PHD87 | ||
| 003 | IN-BhIIT | ||
| 005 | 20191115180629.0 | ||
| 008 | 191115b ||||| |||| 00| 0 eng d | ||
| 040 | _aIN-BhIIT | ||
| 041 | _aeng | ||
| 082 | 0 | 4 |
_a004 _bSAH/M |
| 100 | 1 | 0 |
_aSahoo, Debiprasanna _eauthor _910162 |
| 245 | 1 | 0 |
_aModeling, verification and analysis of DRAM caches / _cby Debiprasanna Sahoo |
| 260 |
_aBhubaneswar : _bIIT Bhubaneswar, _c2019. |
||
| 300 |
_axxix, 153p. : _bill, (some col.) ; _c29cm. |
||
| 504 | _aIncludes bibliographical references and index. | ||
| 650 |
_aElectrical engineering _910163 |
||
| 700 | 1 | 0 |
_aSatpathy, Manoranjan _eguide _910164 |
| 942 | _cTH | ||