| 000 | 00786nam a22002417a 4500 | ||
|---|---|---|---|
| 001 | PHD252 | ||
| 003 | IN-BhIIT | ||
| 005 | 20240226111013.0 | ||
| 008 | 240222b |||||||| |||| 00| 0 eng d | ||
| 040 | _aIN-BhIIT | ||
| 041 | _aeng | ||
| 082 |
_a621.392 _bDHI/A |
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| 100 |
_aDhilleswararao, Pudi. _eAuthor _922486 |
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| 245 |
_aArchitecture and compiler enhancements for silago : _ba CGRA framework for efficient computing / _cby Pudi Dhilleswararao. |
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| 260 |
_aBhubaneswar : _bIIT Bhubaneswar, _c2024. |
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| 300 |
_axv, 184 p. : _b29 cm. |
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| 504 | _aIncluding bibliography and index. | ||
| 650 |
_aLogic circuits. _94964 |
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| 650 |
_aDesign and construction - Data processing. _922495 |
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| 650 |
_aSiLago _922496 |
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| 700 |
_aBoppu, Srinivas. _eGuide _922488 |
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| 942 | _cTH | ||
| 999 |
_c13937 _d13937 |
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