| 000 | 00652nam a22002177a 4500 | ||
|---|---|---|---|
| 999 |
_c10274 _d10274 |
||
| 001 | TB9386 | ||
| 003 | IN-BhIIT | ||
| 005 | 20230728133558.0 | ||
| 008 | 200125b ||||| |||| 00| 0 eng d | ||
| 020 | _a9788126519316 | ||
| 040 | _aIN-BhIIT | ||
| 041 | _aeng | ||
| 082 |
_a621.392 _bPAD/T |
||
| 100 | 1 |
_aPadmanabhan, T. R. _eaurhor _911662 |
|
| 245 | 1 | 0 |
_aDesign through Verilog HDL / _cT. R. Padmanabhan and B. Bala Tripura Sundari |
| 260 |
_aNew Delhi : _bWiley, _cc2004. |
||
| 300 |
_axii, 455p. ; _c24 cm. |
||
| 650 |
_aElectrical and Electronics Engineering _aVHDL _911663 |
||
| 700 |
_aBala Tripura Sundari, B. _eauthor _911664 |
||
| 942 |
_cTB _02 |
||