TY  - BOOK
AU  - Sahoo,Debiprasanna
AU  - Satpathy,Manoranjan
TI  - Modeling, verification and analysis of DRAM caches / 
U1  - 004 
PY  - 2019///
CY  - Bhubaneswar : 
PB  - IIT Bhubaneswar, 
KW  - Electrical engineering
N1  - Includes bibliographical references and index.
ER  -