Dhilleswararao, Pudi. <br/><br/>
Architecture and compiler enhancements for silago :  a CGRA framework for efficient computing / 
by Pudi Dhilleswararao. 
 - Bhubaneswar :   IIT Bhubaneswar,  2024. 
 - xv, 184 p. :  29 cm. 
<br/><br/>Including bibliography and index. 
<br/><br/><label>Subjects--Topical Terms: </label><br/>Logic circuits.<br/>Design and construction - Data processing.<br/>SiLago
<br/><br/><label>Dewey Class. No.: </label>621.392  / DHI/A